Today's electronic devices, as e.g. PDAs, smart phones, web pads or any other kinds of handheld products usually have complete, highly integrated power management units (PMU). These power management units often include a plurality of integrated DC/DC converters. Integrated DC/DC converters are necessary for power efficient supply voltage generation. The battery or power management is real-time software-controlled in order to adapt the system dynamically to different operating conditions.
One of the most often used concepts for DC/DC conversion is the inductive down or up or auto DC/DC converter. In one typical configuration the inductive converter is implemented by four switches, two for the up converting part and two for the down converting part, an inductor and some additional circuitries. The switches are usually implemented by P-type metal oxide silicon field effect transistors (PMOSFET) and N-type metal oxide silicon field effect transistors (NMOSFET) which are integrated on a semiconductor substrate. The integrated circuitry including the MOS transistors is coupled to battery cells (e.g. NiCd/NiMH or Li-Ion/Li-polymer battery pack) and to an inductor via respective pads of the integrated circuitry. Additionally, the integrated DC/DC conversion unit can also comprise a controller circuitry being typically analog or digital. As for all kinds of integrated circuits, the integrated semiconductor devices need protection against excess currents and excess voltages caused by electrostatic discharge (ESD) or electrostatic overstress (EOS). Since the switching NMOS and PMOS transistors of the integrated DC/DC conversion units are to be directly coupled to the external electronic components, known solutions aim to provide direct protection for the transistors.
Accordingly, existing techniques resort for example to adapting the integral properties of the integrated transistors in order to meet ESD requirements. A special manufacturing technique known for example from U.S. Pat. No. 6,858,900 as “un-silicidation” (removal of self-aligned silicide) is used. This technique consists in blocking the deposition of layers of metals like tungsten, titanium or cobalt that are usually used to reduce the access resistance to the drain or source side of a MOS transistor. This measure requires an additional fabrication mask. Additionally, the gate to drain (or source) distance has to be increased, and by doing this a ballast resistor is added due to the higher access resistance of the drain or source diffusions. This leads to smooth flow of ESD current through the drain or source diffusions. However, the main disadvantage of the mentioned technique is that the area consumed by such a protected transistor is considerably increased.
Other known solutions, as for example described in WO 03/094241, provide special layout techniques for adding ballast distributed resistors between the source and the gate as well as the drain and the gate of the integrated MOS devices. In this case the silicide is not removed and the transistor occupies less area. However, this solution requires a special layout technique that is very sensitive to process variations and namely the silicide resistance. The silicide resistance as a process parameter has usually large dispersion in most commercial CMOS processes. And finally, the known solutions can hardly be modeled or simulated, because they are based on the assumption that the transistor will operate in a parasitic bipolar operation regime (snap-back) which is typically not modeled. This renders the behavior of the electronic device very difficult to model. Due to their process dependency, these concepts are also very difficultly portable between different manufacturing processes, but also between fabrication sites.